Towards mechanized verification of Verilog equivalence checking. ~ Michalis Pardalos, Laura Pozzi, John Wickerson. https://johnwickerson.github.io/papers/vera_LATTE25.pdf #ITP #Coq
Towards mechanized verification of Verilog equivalence checking. ~ Michalis Pardalos, Laura Pozzi, John Wickerson. https://johnwickerson.github.io/papers/vera_LATTE25.pdf #ITP #Coq
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