@aleksorsist @whitequark✧✦Catherine✦✧ @urja Lol.

A VLIW processor may actually end up being the logical implementation of this. Who knows.

But the more I think about it, the more I lean towards a two-part system with a bunch of parallel function blocks that output one or more bits every cycle (each block having a bunch of config registers to specify muxing and thresholds and such), then a serial state machine operating on their output.