Fun low level problem: I have two different processors, of different architectures (Cortex-M33 and Cortex-A35). One is 32 bit ARMv7-M, the other aarch64.

They communicate through (among other things) shared access to an internal SRAM that you can use for shared variables, mailbox buffers, etc.

These SRAMs are mapped at the same address on both systems (but obviously zero-padded on the high side on the aarch64 processor).