The last month of my life: BreakingTTAPs

This is a custom transport-triggered, 32 bit processor that will be fabricated by GlobalFoundries on their 180nm process (via of http://wafer.space)

I'll make a video at some point, but some high level details here.

- Transport-triggered architecture
- ~20Mhz
- Two 32 bit data buses (i.e. two instructions per cycle)
- 1024 double slot instruction memory
- 256 word stack
- 4kb of general RAM
- 80 or so various instruction types
- 16 GPIO, SPI, UART, 8 bit parallel memory loader interface

Clock speed is sorta up in the air. Still optimizing, but simulations say it should hit ~20MHz in all "process corners" (i.e. if the fab makes slow transistors and the chip is 125C hot). Probably faster in nominal case but we'll see

Instruction set is pretty standard set of ALU, LSU, comparisons, branching, bit manip, etc. But I snuck in a few fun extras like a pseudorandom number generator, tanh and multiply-and-accumulate to try some light ML inference (rough plan is reservoir computing)

Chip was written in Spade HDL (http://spade-lang.org), which transpiles down to SystemVerilog. That's then fed into a LibreLane build process that turns the verilog into transistors. All open source!

Few tweaks left before the final deadline. Then it's off to the fab and we'll see if it works in three months!

Really hope there isn't a bug in the memory loader, otherwise it'll be DOA and not much to do about it. But even so, was a great learning experience!