not a professional hardware person by any means, but as a compilerer i like the idea that this almost gives you SSA-style infinite vregs at the ISA level, "just" with a limited context window over the most recent instructions

i also wonder if this would make Thumb-2 style variable lengths interesting again. seems more likely an instruction would naturally involve only the most recent N values than a register allocator being happy confined to only N anointed registers
mendeddrum.org/@fanf/114671624

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