@timTim Small
@whitequark✧✦Catherine✦✧
@elly that doesn't implement the SPI flash protocol so you're dependent on the fpga doing translation and then the pin-to-pin latency of the fpga fabric becomes a problem. and based on a skim of the datasheet, it looks like the PSRAM can introduce delays during internal refreshes which breaks the read commands that need predictable latency.
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