so, you know, SPI flashes, right? little eight pin abominations that store a few MB of data.

they normally use three bytes to address said data. this would cap the maximum size at 16 MB. but memory vendors wouldn't be memory vendors if they did not choose to transcend expectations... by inventing 7 (seven) incompatible ways to add the missing fourth byte. and then inventing a standard (JESD216B) with a pair of horrid bitmasks indicating which device supports what.

of note is the fact that the bitmasks for "entering" and "exiting" 4 byte mode are independent. so even though e.g. there is a "Enter 4 Byte Mode" instruction defined in the standard, and also an "Exit 4 Byte Mode" instruction, the devices aren't actually constrained to implementing only both or neither.

i found this funny. the fool. the poor, ignorant, happy fool

the vendors knew what it's about, which is probably why the "Exit 4 Byte Addressing" table is 2 bits wide than the "Enter" table and three of the bits are allocated to three different ways of resetting the device.

(cont'd)