Ah it's actually worse than that https://github.com/riscv/riscv-isa-manual/issues/2396
Today in "RISC-V is incredibly vague about important things": they changed the wording in the spec to imply that writing to one half of `mcycle` or `minstret` suppresses the increment of the other half.
I thought the old wording was pretty clear and I actually had a test that it did *not* do that.
Is it good when the source code for your processor has to reference github issues to clarify spec details?
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